1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and an inspection method of the same. More particular, the present invention relates to a semiconductor integrated circuit device provided with a memory having redundant cells, and an inspection method of the same.
2. Description of the Related Art
In a field of a semiconductor integrated circuit device (LSI), a BIST (Built-in Self Test) is known as a technique aimed at reducing a test time of a memory. According to the technique, a BIST circuit that generates a test pattern for inspection and judges whether an output corresponding to the test pattern can be obtained, is built into a chip in advance. When inspecting the memory, it is detected whether a trouble is present with respect to the memory as a whole by making the BIST circuit operate, and the result is then outputted.
Also, a redundancy method is known as a technique to improve an yield of a memory. According to this technique, redundant cells, and repair word lines and repair bit lines, are provided in a memory cell array in advance. A defective memory cell is repaired, by replacing a word line or bit line connected to the defective memory cell with a repair word line or repair bit line.
Japanese Laid Open Patent Application JP-P2004-310951A discloses a semiconductor integrated circuit device having a repair possibility judgment function for judging whether a memory is repairable or not. The memory has one pair of repair redundant lines in a column direction. A test pattern generation section generates a particular test pattern for the memory. A comparison section reads outputs of the memory, to judge whether or not a defective cell is present in the memory. A first data storage section is used to take a signal inputted from the test pattern generation section to the memory, and a right-and-wrong judgement signal in every bit from the comparison section in testing the memory, and is used to observe an input signal to the memory in testing logic around the memory. A second data storage section inputs an output signal of the comparison section, and shows presence or absence of a failure. In accordance with a value of the second data storage section, a data kept in the first data storage section is held. A repair possibility judgement section judges whether the memory is repairable, based on the input of which is the input to the first data storage section and the output of the first data storage section.
The number of memories built into a single semiconductor chip is increasing in recent years, the number reaching 100 to 200 in some cases. If a test of a memory is separately conducted for each memory, time for inspection is enormous. When ten memories are included in a single chip for example, a test needs to be repeated ten times for the single chip. In addition, the test has to be repeated for whole ten times for almost all chips, since the number of chips having defects is very small. A technique is needed that can reduce a test time of a memory.
According to a semiconductor integrated circuit device and an inspection method of the same, of the present invention, a test time of a memory can be reduced.